1. Field of the Invention
The present invention relates to an output buffer circuit. More particularly, the present invention relates to a slew rate buffer type of an output buffer circuit having a function of controlling a slew rate of an output signal.
2. Description of the Related Art
In general, an output buffer circuit having this type of slew rate control function is used for an output in a signal system, in which a speed is slow, such as a reset signal, a stop signal, a standby signal. The slew rate control function enables the stable operation in which a load circuit receiving the output signal does not suffer from the influence, such as high harmonic noise, ringing.
A conventional type of output buffer circuit is, for example, disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 8-56147) ('147), Japanese Laid Open Patent Application (JP-A-Heisei 4-172012) ('012), Japanese Laid Open Patent Application (JP-A-Heisei 5-191259) ('259), Japanese Laid Open Patent Application (JP-A-Heisei 1-171317) ('317), Japanese Laid Open Patent Application (JP-A-Heisei 5-347545) ('545), Japanese Laid Open Patent Application (JP-A-Heisei 5-114852) ('852) and Japanese Laid Open Patent Application (JP-A-Heisei 6-252723) ('723).
The conventional first output buffer circuit disclosed in the '147 publication will be described below with reference to FIG. 1. The conventional first output buffer circuit is provided with inverters IV1, IV2, a P-channel MOS transistor P1, an N-channel MOS transistor N1, a bias circuit 103, a P-channel MOS transistor P2, an N-channel MOS transistor N2, a bias circuit 104, a slew rate control circuit 101, a slew rate control circuit 102, an output buffer 2, a schmitt trigger ST1 and a schmitt trigger ST2.
The inverters IV1, IV2 are connected in series, and then receive an input signal IN, and further output signals IB, IBB, respectively. In the P-channel MOS transistor P1, a source thereof is connected to a power supply VDD, and a gate thereof is connected to the output of the inverter IV1, respectively. In the N-channel MOS transistor N1, a source thereof is connected to a ground G, and a gate thereof is connected to an output of the schmitt trigger ST1, respectively. The bias circuit 103 is inserted between respective drains of the transistors P1, N1, and then outputs bias voltages B1, B1B.
In the P-channel MOS transistor P2, a source thereof is connected to the power supply VDD, and a gate thereof is connected to an output of the schmitt trigger ST2, respectively. In the N-channel MOS transistor N2, a source thereof is connected to the ground G, and a gate thereof is connected to the output of the inverter IV1, respectively. The bias circuit 104 is inserted between respective drains of the transistors P2, N2, and then outputs bias voltages B2, B2B.
The slew rate control circuit 101 receives the output signal IBB of the inverter IV2 and the bias voltages B1, B1B, and then outputs a slew rate control signal T1. The slew rate control circuit 102 receives the output signal IBB of the inverter IV2 and the bias voltages B2, B2B, and then outputs a slew rate control signal T2. An output buffer 2 outputs an output signal O to an output terminal TO, in response to the supply of the signals T1, T2. The schmitt trigger ST1 sends an output signal S1 to the gate of the transistor N1, in response to the supply of the signal T1. The schmitt trigger ST2 sends an output signal S2 to the gate of the transistor P2, in response to the supply of the signal T2.
The output buffer 2 is provided with a P-channel MOS transistor P21 that is a pull-up transistor and an N-channel MOS transistor N21 that is a pull-down transistor. In the P-channel MOS transistor P21, a source thereof is connected to the power supply VDD, and a drain thereof is connected to the output terminal TO, respectively, and the gate receives the signal T1. In the N-channel MOS transistor N21, a drain thereof is connected to the drain of the transistor P21, and a source thereof is connected to the ground G, respectively, and the gate receives the signal T2.
The slew rate control circuit 101 is provided with a P-channel MOS transistor P101, an N-channel MOS transistor N101, a P-channel MOS transistor P102 and a capacitor C101.
In the P-channel MOS transistor P101, a source thereof is connected to the power supply VDD, and then a gate thereof receives the signal B1, and a drain thereof outputs the signal T1. In the N-channel MOS transistor N101, a drain thereof is connected to the drain of the transistor P101, and a source thereof is connected to the ground G, respectively, and then a gate thereof receives the signal B1B. In the P-channel MOS transistor P102, a gate thereof is connected to the output of the inverter IV2, a source thereof is connected to the power supply VDD, and a drain thereof is connected to the drain of the transistor P101, respectively. The capacitor C101 is connected between the drain of the transistor P102 and the ground G, and then generates a gate capacitance of the transistor P21 in the output buffer circuit 2.
The slew rate control circuit 102 is provided with a P-channel MOS transistor P103, an N-channel MOS transistor N102, an N-channel MOS transistor N103 and a capacitor C102.
In the P-channel MOS transistor P103, a source thereof is connected to the power supply VDD, and then a gate thereof receives the signal B2, and a drain thereof outputs the signal T2.
In the N-channel MOS transistor N102, a drain thereof is connected to the drain of the transistor P103, and a source thereof is connected to the ground G, respectively, and then a gate thereof receives the signal B2B. In the N-channel MOS transistor N103, a gate thereof is connected to the output of the inverter IV2, a source thereof is connected to the ground G, and a drain thereof is connected to the drain of the transistor P103, respectively. The capacitor C102 is connected between the drain of the transistor N102 and the ground G, and then generates a gate capacitance of the transistor N21 in the output buffer circuit 2.
The operations of the conventional first output buffer circuit will be described below with reference to FIG. 2.
At first, suppose that the operations start from a stable state in which the input signal IN and the output signal O are in an L level, that is `0`. At this time, the transistor P21 of the output buffer 2 is in an off-state, and the transistor N21 is in an on-state. This indicates that the signals T1, T2 are `1`.
In accordance with an H level of the signal T2, the input to the schmitt trigger ST2 is also `1`, and then the output signal S2 of the schmitt trigger ST2 is `1`, and further the transistor P2 is in the off-state.
Moreover, since the input signal IN is `0`, the signal IB is `1`, and then the signal IBB is `0`, and thereby the transistor N103 is in the off-state, and the transistor N2 is in the on-state. Accordingly, the bias circuit 104 becomes inactive, and the bias voltages B2, B2B are equal to a potential of the ground G. Thus, the transistor N102 is in the off-state, and the transistor P103 becomes in a linear area and functions as a resistor. Hence, the signal T2 corresponds to a potential of a condition that it is connected through a resistive clamp to the power supply VDD.
Similarly, if the signal T1 is `1`, the input to the schmitt trigger ST1 is `1`, and then the output signal S1 of the schmitt trigger ST1 is `1`, and further the transistor N1 is in the on-state. Moreover, since the input signal IN is `0`, the transistor P1 is in the off-state, and also the transistor P102 is in the on-state. The bias circuit 103 is inactive, and the bias voltages B1, B1B are equal to the potential of the ground G. Accordingly, the transistor N101 is in the off-state, and the transistor P101 becomes in the linear area, and then functions as the resistor. Thus, the signal T1 corresponds to a potential of a condition that it is connected through both the transistor P102 and the transistor P101 to the power supply VDD. The signal T1 corresponds to a potential of a condition that it is connected through a resistive clamp to the power supply VDD.
At first, at a leading edge of the input signal IN, the transistor N103 rapidly discharges a gate capacitance C102 of the pull-down transistor N21, and rapidly turns off this transistor N21. Then, when the signal IB becomes in the L level, the transistor N2 is turned off and meanwhile the potential of the signal T2 becomes equal to or less than a threshold of the schmitt trigger ST2, the transistor P2 is turned on. Although the bias circuit 104 is still inactive, the bias voltages B2, B2B at this time are equal to a value of a voltage of the power supply VDD. Thus, the transistor P103 is turned off, and thereby the transistor N102 is biased in a straight area.
Next, when the signal IB is shifted from `1` to `0`, the transistor P1 is turned on. Since the transistor N1 is in the on-state, the bias circuit 103 is operated. Similarly, the transistor N103 is turned on, and also the transistor P102 is turned on. The bias voltages B1, B1B are in a saturation area, and the transistors P101, N101 are biased therein. Thus, these transistors P101, N101 substantially function as a constant current source and a constant current sink, respectively. A gate capacitance C101 of the transistor P21 is discharged under a substantially constant bias (discharging) current Ib1 which is a difference between respective drain currents of the transistors N101, P101.
When the voltage of the signal T1 becomes equal to or less than about 1/3 times the voltage of the power supply VDD, the state of the schmitt trigger ST1 is shifted, and the transistor N1 is turned off. Thus, the bias circuit 103 is inactive, and the bias voltages B1, B1B are equal to the value of the voltage of the power supply VDD. Accordingly, the transistor P101 is turned off, and the transistor N101 is biased in the straight area. That is, the transistor P101 is gradually changed to the value of the voltage of the ground G from a substantially constant current sink with respect to the resistive clamp. The bias current Ib1 is gradually reduced to 0.
As mentioned above, the bias current Ib1 is substantially constant in a period while the transistor N101 is operated as the substantially constant current sink. Thus, the voltage VT1 of the signal T1 is dropped substantially straight in accordance with a slew rate VSR=dVT1/dt=Ib1/C101. That is, the slew rate VSR of the gate voltage of the transistor P21 is represented by the equation: EQU VSR=VDD/{a.times.(Imax/ISR)}
Here, the ISR is a slew rate of the drain current of the transistor P21. The Imax is a peak value of the drain current of the transistor P21 obtained when the voltage VT1-VDD between the gate and the source of the transistor P21 and the voltage O-VDD between the drain and the source of the transistor P21 are both equal to the voltage VDD. The a is an experimental constant ranging between 1.2 and 1.3 with respect to a sub-micron CMOS process.
Hence, the ISR is represented by the equation: EQU ISR=Ib1.times.(Imax/C101).times.(a/VDD)
It is possible to properly select the discharging current Ib1 to thereby achieve the control of the slew rate ISR of the drain current of the pull-up transistor P21.
Next, at a trailing edge of the input signal IN, the transistor P102 rapidly charges the gate capacitance C101 of the pull-up transistor P21, and rapidly turns off the transistor P21. From this time, the operations similar to the above-mentioned operations except an inversion of a polarity enable the control of the slew rate of the drain current of the pull-down transistor N21.
However, although this conventional first output buffer circuit is effective for a circuit in which the slew rate is relatively fast (approximately several tens nano-seconds), this has a problem that it is difficult to apply to a circuit in which the slew rate is slow (approximately several nano-seconds).
There are two methods described below, as a manner to use the conventional first output buffer circuit to thereby attain a circuit in which the slew rate is slow. For explanatory convenience, as a condition, it is assumed that the bias currents Ib1, Ib2 of the slew rate control circuits 101, 102 are constant.
That is, a first method (1) is a method of making the transistor sizes of the transistors P21, N21 in the output buffer 2 constant and thereby increasing the capacitances of the respective capacitors C101, C102 in the slew rate control circuits 101, 102. A second method (2) is a method of making the capacitances of the respective capacitors C101, C102 in the slew rate control circuits 101, 102 constant and thereby decreasing the transistor sizes of the transistors P21, N21 in the output buffer 2.
However, the first method (1) has a problem that the increase of the capacitances of the capacitors C101, C102 causes a layout area to be extremely larger. Referring to FIG. 2 showing in a time chart the change of a delay time tpd if the transistor size is changed, as the transistor size is decreased in order of A.fwdarw.B.fwdarw.C, the delay time tpd becomes larger in the second method (2). Moreover, a performance of driving the output current (the output signal O) to the output terminal TO is naturally reduced in conjunction with the decrease of the transistor sizes of the transistors P21, N21.
The conventional second output buffer circuit disclosed in the document 2 will be described below with reference to FIG. 3. In FIG. 3, common reference characters/numerals are given to the elements common to those of FIG. 1.
The conventional second output buffer circuit is provided with an output buffer 2, an inverter IV1, a first stage buffer 1, a gate potential control circuit 202, a gate potential control circuit 203 and a delay buffer 204.
The output buffer 2 and the inverter IV1 are respectively common to those of the conventional first output buffer circuit. The first stage buffer 1 is composed of a P-channel MOS transistor P11 and an N-channel MOS transistor N11. A current supply performance thereof is smaller than that of the output buffer 2. The gate potential control circuit 202 controls a gate potential of a pull-up transistor P21 of the output buffer 2, in accordance with an input level IN. The gate potential control circuit 203 controls a gate potential of a pull-down transistor N21 of the output buffer 2, in accordance with the input level IN.
The operations of the conventional second output buffer circuit will be described below.
When the input level IN is a level of the ground G, a signal IB is in the H level. Thus, N-channel MOS transistors N202, N204 of the gate potential control circuits 202, 203 are in the on-state, and P-channel MOS transistors P202, P204 are in the off-state. Hence, a signal G1 is in the ground G level equal to a potential of the input signal IN, and a signal G2 is in the ground G level equal to a potential of an output signal O. Signals T, T2 become both in the H level. Accordingly, the transistor P21 is in the off-state, and the transistor N21 is in the on-state.
Next, when the input signal IN rises up on a side of the H level, the transistors N202, N204 become in the off-state, and the transistor P204 becomes in the on-state. At this time, the transistor P202 is in the off-state until the level of the output signal O becomes higher than the signal G1 by a threshold voltage VT of the transistor P202. The potential of the signal G1 is kept in the potential of the ground G, until the delay buffer 204 switches the first stage buffer 1. Similarly, the signal T1 is located on the side of the high potential, and the transistor P21 is also in the off-state.
The potential of the signal G2 is shifted to the side of the H level, and the signal T2 becomes in the L level. Thus, the transistor N21 is turned off. At this time, the output of the buffer 204 is shifted from the side of the H level to the side of the L level. The transistors P21, N21 of the output buffer 2 are both in the off-state until the first stage buffer 1 is switched.
When the output of the buffer 204 is shifted from the H level to the L level and the first stage buffer 1 is switched, the transistor P11 is shifted from the off-state to the on-state, and the transistor N11 is shifted from the on-state to the off-state, respectively. Then, the output signal O is shifted from the ground potential G level to the H level. At this time, the current supply performances of the transistors P11, N11 are small. Hence, a penetrating current is small, and the generation of power supply noise is also small.
Next when the potential of the output signal O becomes higher than that of the signal G1 by a value of a threshold voltage of the transistor P202, the transistor P202 is turned on. When the level of the signal G1 reaches a threshold of an inverter provided with the transistors P203, N203, the signal T1 is shifted from the H level to the level of the ground G, and the transistor P21 becomes in the on-state. The current supply performance at this time is a value equal to the sum of the transistors P21 and P11.
When the input signal IN is dropped from the H level to the ground level G, the transistor P21 becomes in the off-state. When the first stage buffer 1 is switched, the potential of the output signal O is shifted from the H level to the ground level G by the transistor N11. When the potential of the output signal O reaches a threshold of an inverter provided with the transistors P205, N205, the signal T2 is shifted from the L level to the H level, and the transistor N21 becomes in the on-state.
The conventional third output buffer circuit disclosed in the 259 publication will be described below with reference to FIG. 4. In FIG. 4, common reference characters/numerals are given to the elements common to that of FIG. 3.
As shown in FIG. 4, the conventional third output buffer circuit is provided with a first stage buffer 1, an output buffer 2, an inverter IV1, an supplementary drive circuit 301 and a supplementary drive circuit 302. The first stage buffer 1, the output buffer 2 and the inverter IV1 are respectively common to those of the conventional second output buffer circuit.
The supplementary drive circuit 301 switches a gate signal of a transistor P21 to any one of the L level and the delay signal when an input signal is shifted, under the control of a control signal M1. The supplementary drive circuit 302 switches a gate signal of a transistor N21 to any one of the H level and the delay signal when the input signal is shifted, under the control of a control signal M2. The supplementary drive circuit 301 and the supplementary drive circuit 302 are provided instead of the gate potential control circuits 202, 203 of the conventional second output buffer circuit.
This conventional third output buffer circuit is operated such that instead of the gate potential control circuits 202, 203, the supplementary drive circuits 301, 302 relax the transient phenomenon occurring at the time of the level shift in the input signal IN, and the power supply noise occurring at the time of the level shift in the output is suppressed in the case of the large current drive.
The conventional fourth output buffer circuit disclosed in the 317 publication will be described below with reference to FIG. 5. In FIG. 5, common reference characters/numerals are given to the elements common to that of FIG. 3.
The conventional fourth output buffer circuit is provided with an exclusive-OR circuit 401, in addition to the first stage buffer 1, the output buffer 2 and the delay buffer 204 which are common to those of the conventional second output buffer circuit.
The exclusive-OR circuit 401 carries out an exclusive-OR operation of the output signal of the delay buffer 204 and the input signal IN, and then generates an inversion input signal T1 of the output buffer 2. The operations, especially, the operations of the first stage buffer and the output buffer are substantially identical to those of the conventional second and third output buffer circuits. Thus, the explanations thereof are omitted.
However, if the conventional second, third and fourth output buffer circuits try to attain the characteristic of the low slew rate targeted by the present invention, this results in a problem that the dispersions of the on-resistances of the transistors and the like cause the dispersion of the slew rate to be larger.
For example, when considering the first stage buffer 1 as an example, it is necessary to set the respective on-resistances of the P-channel MOS transistor P11 and the N-channel MOS transistor N11 constituting this first stage buffer 1 to be larger, in order to make the slew rate slower, that is, lower.
On the other hand, as the on-resistance is higher, it receives the influences of the dispersions of a voltage of a power supply, a temperature, a manufacturing process and the like. It causes the dispersion of approximately 50% with respect to a central value, as an example. This dispersion is directly reflected as the dispersion of the slew rate. Moreover, in all the cases of the conventional second, third and fourth output buffer circuits, the output terminal of the first stage buffer 1 is directly connected to the output terminal of the output buffer 2 in parallel. Thus, the dispersion of the slew rate in the first stage buffer 1 is directly reflected in the dispersion of the slew rate of the output signal O.
The conventional first output buffer circuit is essentially the buffer circuit for the fast operation. Thus, in order to achieve the circuit having the low slew rate, it is necessary to employ any one of the method of making the gate capacitances of the respective transistors in the output buffer larger and the method of making the sizes of the respective transistors in the output buffer smaller to thereby make the driving performance lower. The former case causes the area occupied by the capacitor for the gate capacitance addition to be increased. The latter case causes the delay time to be longer, and also causes the load current driving performance to be smaller. This results in a defect that it is difficult to attain the circuit having the low slew rate.
If the conventional second, third and fourth output buffer circuits try to achieve the performance of the low slew rate, it is necessary to set the on-resistances of the transistors constituting the buffer circuit to be higher. Thus, it easily receives the influences of the dispersions of the voltage of the power supply, the temperature and the manufacturing process. This leads to a defect that the dispersion of the slew rate is larger. Moreover, the respective output terminals of the first stage buffer 1 and the output buffer 2 are directly connected parallel to each other, which results in a defect that the dispersion of the slew rate in the first stage buffer 1 is directly reflected as the dispersion of the slew rate in the output signal.
The following configuration is disclosed in an output buffer of a semiconductor integrated circuit noted in the 545 publication. That is, a P-channel MOS transistor P11 at a final stage of the output buffer is connected to a supplementary P-channel MOS transistor P12 in parallel to each other. An N-channel MOS transistor N11 is connected to a supplementary N-channel MOS transistor N12 in parallel to each other. Then, supplementary control circuits G12, G13 each composed of NAND gates or NOR gates and a delay circuit for controlling these supplementary MOS transistors are provided therein.
The following configuration is disclosed in a small noise output drive circuit noted in the 852 publication. That is, it includes a first drive circuit having on a power supply side a MOSFET for reducing a value corresponding to a threshold voltage in which a gate and a drain are connected to each other, and a second drive circuit having a typical structure composed of CMOS inverters. The operation is controlled by a delay control circuit so that the first drive circuit is firstly driven and the second drive circuit is next driven. According to this configuration, in the first drive circuit, a voltage drop corresponding to the threshold voltage leaves therein, and accordingly it does not shake up to a potential of the power supply. After it reaches the potential of the power supply in the second drive circuit. This method can suppress an excessive transient current when the output is changed. Moreover, this method can solve an overshoot and an undershoot.
The following configuration is disclosed in a load drive circuit noted in the 723 publication. That is, it includes a control device which in the load drive circuit for connecting a load to a power supply in an output section of a CMOS circuit, when mutually turning on and off a P-channel MOS transistor and an N-channel transistor constituting the CMOS circuit, turns off both the transistors for a predetermined period.